Memory - NAND & DRAM Subscriptions
Our analysis quantifies the unknown to help you make informed design and business decisions.
Huge up-front R&D investment requires customers to have up-to-date and accurate competitive intelligence.
We can determine what it will cost to bring advanced memory to market, we research potential market challenges to help you determine what your risks are, and we help define your de-risking strategy.
The Memory - NAND & DRAM Advantage
TechInsights Memory offerings have been developed to provide the focused technical intelligence you need based on your industry and role.
Memory - NAND & DRAM Channels
- Provide cost-effective competitive analysis to guide strategic decisions in a given focus area
- Identify market challenges and risks and define your de-risking strategy
- Deliver an understanding of what it will cost to bring advanced memory to market
Executive summary supported with image sets
- Process node and foundry identification
- Critical dimensions
- Functional block summary
- Stacked optical top metal and poly die photo delivered in CircuitVision. Includes calibrated measurement and annotations tools
- SEM cross-sectional and bevel imaging
- 13-15 reports/year
Transistor Characterization Report (TCR)
- Universal curves for IOFF vs. ION and IOFF vs. ID, LIN derived from
- 5 NMOS and 5 PMOS sub wordline driver transistors, across multiple VDD at 85°C
- 5 NMOS and 5 PMOS sense amp transistors, across multiple VDD at 85°C
- For each universal curve data point
- Transistor Characteristics: ID, SAT, ID, Lin, Ioff, VT, Lin & VT, SAT, ΔVGS, Gm, SS, DIBL
- Output Characteristics
Analysis Coverage
- 4 reports/year
- Trend Analysis
- 4 hrs support
Concise analyst’s summary of critical device metrics
- Circuit schematic diagram of sense amplifier
- Circuit schematic diagram of a sub wordline driver
- Detailed stacked SEM images of a delayered DRAM sense amplifier and sub wordline driver delivered in CircuitVision. Includes calibrated measurement and annotation tools
- ~4 reports/year
Full Circuit Analysis
- 1 – Memory Array and Peripherals
- 2 – Address Path
- 3 – Data Path
- 4 – Control Blocks, Configuration and Test Block
- 5 – Voltage Generators System
Analysis Coverage
- Full 2/year
Analysis Coverage
- Executive summary supported with image sets
- Process Node and Foundry Identification
- Critical Dimensions
- Functional Block Summary
- Stacked optical top metal and poly die photo delivered in CircutVision which includes calibrated measurement tools
- SEM cross-sectional imaging
- 13-15 reports/year
Concise analyst’s summary of critical device metrics
- Circuit schematic diagram of a page buffer: decoder, switch, and controller
- Circuit schematic diagram of a wordline driver: decoder and switch
- Detailed stacked plan view SEM images of a beveled NAND page buffer and wordline driver delivered in CircuitVision. CircuitVision includes calibrated measurement and annotation tools
- ~4 reports/year
Full Circuit Analysis
- 1 – Memory Array and Peripherals
- 2 – Address Path
- 3 – Data Path
- 4 – Control Blocks, Configuration and Test Block
- 5 – Voltage Generators System
Full Circuit Analysis
- Full 2/year
This channel examines the waveforms used on NAND memory cells during program, read and erase cycles.
- Delivers 8 reports over a 12-month period as well as an online seminar
- Provides a Waveform summary PDF and raw waveform .sht files to enable the customer to perform further analysis and measurements
Advanced Memory Essentials (AME)
- Focused on leading edge NAND and DRAM memory technology
- Executive summary supported by large image sets
- SEM cross-sectional and bevel imaging
- TEM cross-sectional analysis with TEM EDS
- 8 reports/year
Analysis Coverage
- Technical trend/roadmap by technology element
- Design technology interaction analysis
- Detailed explanation of process integrations
- Next node predictions
- 3 briefings/year
- Trend analysis
- Forecasting
- 1 annual seminar
- 4 hrs support
(Requires Advanced Process Subscription)
Process Flow Analysis (PFA)
- Spreadsheets showing process, architecture, mask list, and integration-level process steps
- 8 Memory / year
Process Flow Full Emulation (PFF)
- PFA content may be updated
- Layout GDS fully decomposed into process layers
- 3D Emulation
- Synopsys Input (Route-Level Deck)*
*Requires Synopsys license to view and modify - 6 Memory / year
Analysis Coverage
- Cell Design technology interaction analysis
- Detailed explanation of process integration from wafer-in through wafer-out
- Process steps, materials, equipment type, unit process
- SEM and TEM cross-sectional and top-view images
- Layer annotations, specific process module, assumption
- Trend analysis
- +4 hrs support
- 4 NAND devices analyzed per year
- Cross-technology analysis and 4 hours support per year
- 10 types of transistors characterized at 85°C for each NAND device
- Transistor types:
- Peripheral High Voltage(HV) CSL Driver Transistor
- Page Buffer HV BLSLT NMOS Transistor
- Page Buffer HV BLGIDL NMOS Transistor
- XDEC NMOS Pass Transistor
- XDEC HV Depletion Transistor
- XDEC HV PMOS Transistor
- Page Buffer Mid Gox NMOS Transistor
- Page Buffer Mid Gox PMOS Transistor
- I/O Mid Gox NMOS Transistor
- I/O Mid Gox PMOS Transistor
- Test results for each transistor type will includes plots for: Transfer function, Output function, Body effect, Breakdown voltage, Transconductance (gm), Threshold voltage (VT), and Subthreshold swing (SS).
- Raw data files for all measured transistors will be included.
Related Resources

Memory Technology Trends and Challenges
January 30, 2023

Hybrid Bonding Technology - 2023 and beyond
January 30, 2023

The Continuously Evolving Landscape of Memory Technology
January 24, 2023
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