Intel 10 nm Logic Process Analysis (Cannon Lake)

Posted: June 12, 2018

Intel 10nm Logic Process Analysis

TechInsights has found the long-awaited Cannon Lake - the Intel 10 nm logic process inside the i3-8121U CPU, used in the Lenovo IdeaPad330.

This innovation boasts the following:

Logic transistor density of 100.8 mega transistors per mm², increasing 10nm density 2.7X over the 14nm node
Utilizes third generation FinFET technology
Minimum gate pitch of Intel’s 10 nm process shrinks from 70 nm to 54 nm
Minimum metal pitch shrinks from 52 nm to 36 nm

Process Highlights:

Design Highlights:

Related Analysis	Manufacturer	Analysis Type	Subscription Channel
Intel i3-8121U Cannon Lake Intel 10 nm FinFET Process Digital Functional Analysis	Intel	Floorplan	Logic - Digital Floorplan
Intel i3-8121U Cannon Lake Intel 10 nm SoC Overhead Layout Analysis DDR I/O to CPU Transition Region Standard Cell Essentials	Intel	Process	Logic - SoC Design Analysis
Intel i3-8121U Cannon Lake Intel 10 nm FinFET Process Advanced CMOS Essentials - Part 1	Intel	Process	Logic - Process
Intel i3-8121U Cannon Lake Intel 10 nm Transistor Characterization	Intel	Functional - Testing	Logic - Transistor Characterization
Intel i3-8121U Intel 10 nm CPU 9.27-Track Standard Cell Essentials	Intel	Process	Logic - SoC Design Analysis
Intel i3-8121U Intel 10 nm GPU 6.18-Track Standard Cell Essentials	Intel	Process	Logic - SoC Design Analysis
Intel i3-8121U Cannon Lake Intel 10 nm FinFET Process Advanced CMOS Essentials - Part 2	Intel	Process	Logic - Process