DRAM: SWD and Sense Amp Transistor Characterization

Includes:

• Transitor Characterization Report (TCR)
  • Universal curves for IOFF vs. ION and IOFF vs. ID, LIN derived from
    • 5 NMOS and 5 PMOS sub wordline driver transistors, across multiple VDD at 85°C
    • 5 NMOS and 5 PMOS sense amp transitors, across multiple VDD at 85°C
  • For each universal curve data point
    • Transistor Characteristics: I_{D, SAT}, I_{D, Lin}, I_off, V_{T, Lin} & V_{T, SAT}, ΔV_GS, G_m, SS, DIBL
    • Output Characteristics
• Analysis Coverage
  • 4 reports/year
  • Trend Analysis
  • 4 hrs support

DRAM: Circuit Analysis

Includes:

• Full Circuit Analysis
  • 1 - Memory Array and Peripherals
  • 2 - Address Path
  • 3 - Data Path
  • 4 - Control Blocks, Configuration and Test Block
  • 5 - Voltage Generators System
• Select Blocks Circuit Analysis
  • 1 - Memory Array and Peripherals
  • 3 - Data Path
  • 5 - Voltage Generators System*
    *Depending upon events and customer interest, TechInsights may produce 1 Select Blocks Circuit Analysis including blocks (1, 3, 5) or 2 Select Blocks Circuit Analysis including blocks (1, 3)
• Analysis Coverage
  • Full 1/year
  • Select Blocks 1/year

NAND Periphery Design (MDP): Page Buffer, Wordline Driver

Includes:

• Concise analyst's summary of critical device metrics
  • Circuit schematic diagram of a page buffer: decoder, switch, and controller
  • Circuit schematic diagram of a wordline driver: decoder and switch
  • Detailed stacked plan view SEM images of a beveled NAND page buffer and worline driver delivered in CircuitVision. CircuitVision includes calibrated measurement and annotation tools
  • ~4 reports/year

Process Flows

*Requires Advanced Process Subscription

Includes:

• Process Flow Analysis (PFA)
  • Spreadsheets showing process, architecture, mask list, and integration-level process steps
  • 8 Memory / year
• Process Flow Full Emulation (PFF)
  • PFA content may be updated
  • Layout GDS fully decomposed into process layers
  • 3D Emulation
  • Synopsys Input (Route-Level Deck)*
    *Requires Synopsys license to view and modify
  • 6 Memory / year
• Analysis Coverage
  • Cell Design technology interaction analysis
  • Detailed explanation of process integration from wafer-in through wafer-out
  • Process steps, materials, equipment type, unit process
  • SEM and TEM cross-sectional and top-view images
  • Layer annotations, specific process module, assumption
  • Trend analysis
  • +4 hrs support

Embedded & Emerging Process Analysis

Includes:

• Analysis Coverage
  • Focused on leading-edge embedded and emerging memory
  • Executive summary supported by large image sets
  • SEM cross-sectional and bevel imaging
  • TEM cross-sectional with TEM EDS
  • Technical trend/roadmap by technology element
  • Design technology interaction analysis
  • Detailed explanation of process integrations
  • Next node predictions
  • 4 reports/year
• Trend Analysis - 1 briefing / year
• Forecasting
• Q&A